Analog layout engineer for memory ips
AustriaChipright
...test chips• Proficient with Cadence design and layout environment• Coordinate Tapeout procedure for internal and external Foundries• Main layout focus: Memories and Supporting Blocks, ADC/DAC, Testchip placement• Knowledge of Layout XL, Calibre/Assura is a plus• Adapt IP blocks and support integration [...]
Kategorie Marketing