Principal engineer digital design (f/m/div)
VillachInfineon Technologies AG
...architecture and RTL implementation through synthesis, power-intent closure (UPF/IEEE 1801), and tape-out. Your work will directly shape how Infineon's AURIX and PSoC microcontroller families manage power domains, control DC/DC regulation loops, handle power sequencing, and meet the strictest functional safety requirements of [...]
Kategorie Medien / Verlag / Redaktion