Staff engineer mixed signal layout (f/m/div)
VillachInfineon Technologies AG
...blocks and high-speed SerDes components Layout Optimization: Implement precise matching techniques and isolation strategies to prevent noise coupling in sensitive analog front-ends Physical Verification: Run and debug full-chip physical verifications including DRC, LVS, ERC, and Antenna rule checks Parasitic Management: Analyze [...]
Kategorie Recht